1. Field of the Invention
The present invention relates to an internal potential generating circuit for generating an internal potential and a boosted potential generating unit contained in a semiconductor device. More specifically, it relates to an internal potential generating circuit and a boosted potential generating unit capable of reducing power consumption.
2. Description of the Background Art
FIG. 29 is a circuit diagram showing details of a boosted potential generating circuit as a conventional internal potential generating circuit.
FIG. 30 is a timing chart showing the operation of the conventional boosted potential generating circuit shown in FIG. 29.
Referring to FIGS. 29 and 30, the operation of the conventional boosted potential generating circuit of FIG. 29 will be described. It is assumed that before time ta, the potential at an input node N1 is at the ground potential GND and the potential at an intermediate node N2 is at the power supply potential Vcc. Switches S2 and S3 are off. At time ta, when a clock .phi.1b at the GND level is input to the gate of a PMOS transistor M1b, a clock .phi.1a at the GND level is input to the gate of an NMOS transistor M1a. Therefore, the potential at input node N1 attains to the power supply potential Vcc. The potential at intermediate node N2 attains to 2Vcc because of capacitive coupling by capacitor C1.
Then, when switch S3 turns on, charges corresponding to 2Vcc-Vpp are injected to a boosted potential node Npp. That is, the first charge injection occurs. Here, if an electrode 48 opposing to the boosted potential node Npp is at the ground potential GND, charges corresponding to (2Vcc-Vpp).multidot.C move from the node having the power supply potential Vcc to the electrode (ground potential GND) opposing to the boosted potential node Npp through PMOS transistor M1a, input node N1, capacitor C1, intermediate node N2 and switch S3. In other words, charges corresponding to 2Vcc-Vpp are consumed. This is the first charge consumption. Here, C represents capacitance of capacitor C1.
At time tb, when the clock .phi.1a at the Vcc level is being input to the gate of NMOS transistor M1a and the clock .phi.1b at the Vcc level is input to the gate of PMOS transistor M1b, the potential at input node N1 attains to the ground potential GND. The potential at intermediate node N2 lowers from boosted potential Vpp by the power supply potential Vcc, because of capacitive coupling of capacitor C1. More specifically, the potential at intermediate node N2 attains to Vpp-Vcc. Here, switch S3 turns off before time tb.
After time tb, switch S2 is turned on. Therefore, charges corresponding to (2Vcc-Vpp).multidot.C move from the node having the power supply potential Vcc to the node having the ground potential GND through switch S2, intermediate node N2, capacitor C1, input node N1 and NMOS transistor M1b. More specifically, charges corresponding to 2Vcc-Vpp are consumed. This is the second charge consumption.
At time tc, the next cycle starts. In other words, one cycle is completed from time ta to tc. Switch S2 is turned off before time tc.
In summary, charges corresponding to 2C.multidot.(2Vcc-Vpp) are consumed in one cycle, and charges corresponding to 2Vcc-Vpp are supplied to the boosted potential node Npp. Therefore, charge efficiency is one half, that is, 50%.
Here, the charge efficiency is 50%. Therefore, when charges I are to be supplied to the boosted potential node Npp in one cycle, charges corresponding to 2I are necessary. Accordingly, in order to supply charges I to the boosted potential node Npp, power consumption of 2I.multidot.Vcc is necessary. From the foregoing, it can be understood that power consumption can be reduced if the charge efficiency is improved.
FIG. 31 is a circuit diagram showing details of a substrate potential generating circuit as a conventional internal potential generating circuit.
Referring to FIG. 31, the conventional substrate potential generating circuit includes a PMOS transistor M1a connected between a node having the power supply potential Vcc and an input node N1; an NMOS transistor M1b connected between input node N1 and a node having the ground potential GND; a capacitor C1 connected between input node N1 and an intermediate node N2; a PMOS transistor M3 connected between a substrate potential node Nbb and intermediate node N2; and a PMOS transistor M2 connected between intermediate node N2 and the node having the ground potential GND. PMOS transistors M1a, M2, M3 and NMOS transistor M1b are controlled by clocks .phi.1a, .phi.2, .phi.3 and .phi.1b, respectively.
FIG. 32 is a timing chart showing the operation of the conventional substrate potential generating circuit shown in FIG. 31.
Clocks .phi.1a and .phi.1b have an amplitude of Vcc. Assume that before time taf, input node N1 is at the ground potential GND and intermediate node N2 is at the substrate potential Vbb.
At time taf, clock .phi.1b is set to the ground potential GND, and NMOS transistor M1b is turned off. At time ta, clock .phi.1a is set to the ground potential GND and PMOS transistor M1a is turned on. As a result, the potential at input node N1 attains to the power supply potential Vcc. The potential at intermediate node N2 is boosted to Vbb+Vcc by the capacitive coupling of capacitor C1.
At time tad, clock .phi.2 is set to -Vcc, and PMOS transistor M2 is turned on. Charges at intermediate node N2 is discharged to the node having the ground potential GND. At this time, charges corresponding to (Vcc+Vbb).multidot.C, that is, charges corresponding to (Vcc-.vertline.Vbb.vertline.) move from the node having the power supply potential Vcc to the node having the ground potential GND, through PMOS transistor M1a, input node N1, capacitor C1, intermediate node N2 and PMOS transistor M2. Namely, charges corresponding to (Vcc+Vbb).multidot.C are consumed. Here, C represents the capacitance of capacitor C1.
At time tbf, clock .phi.1a is set to the power supply potential Vcc, and PMOS transistor M1a is turned off. At time tb, clock .phi.1b is set to the power supply potential Vcc and NMOS transistor M1b is turned on. As a result, the potential at input node N1 attains to the ground potential GND. The potential at intermediate node N2 lowers from the ground potential GND to -Vcc by the capacitive coupling of capacitor C1.
At time tbd, clock .phi.3 is set to -Vcc, and PMOS transistor M3 is turned on. Intermediate node N2 is charged to the substrate potential Vbb. At this time, charges corresponding to (Vcc+Vbb).multidot.C move from the electrode (ground potential GND) opposing to substrate potential node Nbb to the node having the ground potential through substrate potential node Nbb, PMOS transistor M3, intermediate node N2, capacitor C1, input node N1 and MOS transistor M1b. Here, charges corresponding to -(Vcc+Vbb).multidot.C are discharged to the substrate potential node Nbb. This is supply of charges to the substrate potential node. However, since this is the movement of charges from a node having the ground potential GND to another node having the ground potential GND, no power is consumed.
At time tcf, the next cycle starts. In other words, operation of one cycle completes from time taf to time tcf.
In summary, the total charges consumed from the node having the power supply potential Vcc to the node having the ground potential GND in one cycle correspond to (Vcc+Vbb).multidot.C. The substrate potential Vbb has a negative value. Meanwhile, the charges supplied to substrate potential node Nbb is -(Vcc+Vbb).multidot.C. Therefore, charge efficiency is 100%.
Since the charge efficiency is 100%, when charges I are to be injected to the substrate potential node Nbb in one cycle, charges I are consumed. Therefore, when charges I are injected to substrate potential node Nbb in one cycle, the power of I.multidot.Vcc is consumed. From the foregoing, it can be understood that power consumption can be lowered by improving charge efficiency.
As described above, in the conventional boosted potential generating circuit, charge efficiency is 50%. The charge efficiency of the conventional substrate potential generating circuit is 100%.
Therefore, in order to realize lower power consumption, it is required to improve the charge efficiency of the boosted potential generating circuit to be higher than 50%, and to improve the charge efficiency of the substrate potential generating circuit to be higher than 100%.